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Novel Quantum Cost Efficient D Flip-Flop and D Latch

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a fault tolerant reversible logic has gained Importance as they consume low power and less heat Dissipation. The benefits of logical reversibility can be gained only after employing physical reversibility. Every future Technology will have to use reversible gates in order to reduce Power. In this paper, a new fault tolerant reversible 4*4 RR-gate which satisfies the reversible and parity preserving properties. The D-latch and D-flip flop is designed using proposed 4*4 RR-gate fault tolerant reversible gate. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The proposed design is more efficient than the existing designs In terms of power, delay and power delay product..
Keywords: reversible logic, fault tolerant reversible Logic, fan-out, power, delay, power delay product.
According to Landauer’s principle, the loss of one bit of information dissipates kTln2 joules of energy where k is the Boltzmann’s constant and T is the absolute temperature at which the operation is performed [4]. Later Bennett, in 1973, showed that in order to avoid kTln2 joules of energy dissipation in a circuit it must be built from reversible circuits [5]. In 1965 Gordon Moore observed that the performance of integrated circuit would continue to improve at an exponential rate with the performance per unit cost increasing by a factor of 2, every 18 months. According to Gordon Moore [2], shrinking the dimensions on integrated structures makes it possible to operate the structure at a higher speed for the same power per unit area.
As more and more components are getting packed onto the chip, power dissipation in the present day computer is becoming very high. Reversibility in computing implies that no information about the computational states can ever be lost, so we can recover any earlier stage by computing backwards or un-computing the results. This is termed as logical reversibility. The benefits of logical reversibility can be gained only after employing physical reversibility.
Absolutely perfect physical reversibility is practically unachievable.although the various table text styles are provided. The formatter will need to create these components, incorporating the applicable criteria that follow.Computing systems give off heat when voltage levels change from positive to negative: bits from zero to one. Most of the energy needed to make that change is given off in the form of heat. Rather than changing voltages to new levels, reversible circuit elements will gradually move charge from one node to the next. This way, one can only expect to lose a minute amount of energy on each transition. Reversible computing strongly affects digital logic designs. Reversible logic elements are needed to recover the state of inputs from the outputs [4]. Information is lost when the circuit implements nondirective functions. Therefore, in irreversible logic circuit the input vector cannot be recovered from its output vectors. Reversible logic circuit by definition realizes only those functions having one-to-one mapping between its input and output assignments. Hence in reversible circuits no information is lost. Zero energy dissipation would be possible only if the network consists of reversible gates [5].
Perkowski’s states ―every future technology will have to use reversible gates in order to reduce power. This has led many people to pursue research in the area of reversible logic [6]. As all the fault tolerant gates are reversible gates which full fill the reversible logic condition along with the parity preserving fault tolerant property. Fault tolerance enables a system to continue its operations correctly when an error occurs in some parts of it. Detection and correction of errors is so convenient when the components of system are fault tolerant. In communication and many other systems parity will lead to fault tolerance.
A gate is called reversible if there is a one to one correspondence between its input and output patterns. Fan out is not allowed. A logic gate is reversible if the mapping of inputs to outputs is injective, that is, every distinct input pattern a distinct output pattern will be produced, and equal no of input and output are available. Realization of reversible function using gates with smaller width increases the gate count and garbage outputs. Therefore, there must be trade-offs of using a family of reversible gates. There are many reversible gates in the literature. Among them are 2*2 Feynman Gate (FG) [3], 3*3 Peres Gate (PG) [4], 3*3 Toffoli Gate (TG) [7], 3*3 Fred kin Gate (FRG) [8], 3*3 Khan Gate (NG) [7], 3*3 double Gate (F2G) [5], and 3*3 NFT [9]. Any realization techniques should keep both the number of constants and garbage’s as low as possible [8]. Garbage Outputs, Constant Inputs, Gate Count, Hardware Complexity, Area Consumption, Path Delay should be made minimum.


  1. C.H. Bennett / Studies” In History and Philosophy of Modern Physics” 34 (2003) 501-510.
  2. Gordon E. Moore, “Cramming More Components Onto Integrated Circuits”, Electronics, Volume 38, Number 8, April 19, 1965.
  3. Himanshu Thapliyal and Nagarajan Ranganathan.” 2010 Design Of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, And Garbage Outputs” Acm journal On Emerging Technologies In Computer Systems, Vol. 6,No. 4, Article 14, Pub. December.
  4. Himanshu Thapliyal and M.B Srinivas“A Beginning in the Reversible Logic Synthesis of Sequential Circuits”MAPLD 12005/1012.
  5. Himanshu Thapliyal,, and Nagarajan Ranganathan “Reversible Logic-Based Concurrently Testable Latches for Molecular QCA”, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 1, JANUARY 2010.
  6. J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, and X. Li “Efficient Adder Circuits Based On A Conservative Reversible Logic Gate” IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA 2002 IEEE.
  7. Kartikeya Bhardwaj, Bharat M. Deshpande “K-Algorithm: An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier” 26th International Conference on VLSI Design and the 12th International Conference on Embedded Systems 2013.
  8. Kamalika Datta, Indranil Sengupta, Hafizur Rahaman,“Group Theory based Reversible Logic Synthesis” 5th International conference on computer and devices for communication 2012.
  9. Landau, L. D., AndLifshitz, E. M. (1960). “Mechanics. Pergamon Press, New York”.
  10. Rakshith TR. Rakshith Saligram, “Design 0f High Speed Low Power Multiplier using Reversible logic: a Vedic Mathematical Approach”, International Conference on Circuits, Power and Computing Technologies, 2013.
  11. Rakshith Saligram, Rakshith T.R, “Optimized Reversible Vedic Multipliers for HighSpeed Low Power Operations”, IEEE Conference on Information and Communication Technologies 2013.
  12. Sk Noor Mahammad, Siva Kumar SastryHari, Shyam Shroff And V Kamakoti1„‟Constructing Online Testable Circuits Using Reversible Logic‟‟ Reconfigurable And Intelligent Systems Engineering Group, Dept. of Computer Science &Engg. IIT Madras, Chennai.
  13. Yvan van, Rentergem and Alexis de vos“Optimal Design of a Reversible Full Adder”Int. Journ. of Unconventional Computing, Vol. 1, Pp. 339–355 .