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Design of Novel FIR Filter Using Add and Shift Multiplier and Carry Save Adder

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This project investigates the implementation of a low power FIR filter using Add and Shift Multiplier and Carry Save Adder. This method is used to reduce the dynamic power consumption, Delay and Area of a low power FIR filter. This method include Modified Booth Encoding Algorithm combined with Spurious Power Suppression Technique, Low Power Digital Serial Multiplier along with carry look ahead adder, shift and add multiplier. This proposed FIR filter was synthesized and implemented using Xilinx ISE V7.1 and also the power is analyzed using Xilinx XPoweranalyzer.
The impulse response of the filter can be either finite or infinite. The methods for designing and implementing of these two filter classes differ considerably. Finite impulse response (FIR) filters are digital filters whose response to a unit impulse (unit sample function) is finite in duration. This is in contrast to infinite impulse response (IIR) filters whose response to a unit impulse (unit sample function) is infinite in duration. FIR and IIR filters each have advantages and disadvantages. FIR filters can be implemented using either recursive or non-recursive techniques, but usually nonrecursive techniques are used. FIR filters are widely used in various DSP applications. In some applications, the FIR filter circuit must be able to operate at high sample rates, while in other applications the FIR filter circuit must be a low-power circuit operating at moderate sample rates.
The low-power or low-area techniques developed specifically for digital filters. Parallel (or block) processing can be applied to digital FIR filters to either increase the effective throughput or reduce the power consumption of the original filter. Traditionally, the application of parallel processing to an FIR filter involves the replication of the hardware units that exist in the original filter. The topology of the multiplier circuit also affects the resultant power consumption. They extensively use a modified common sub expression elimination algorithm to reduce the number of adders. They have proposed a novel approach for a design method of a low power digital baseband processing. Their approach is to optimize the bit-width of each filter coefficient. They define the problem to find optimized bit-width of each filter coefficient. This project presents the method to reduce dynamic switching power of a fir filter using data transition power diminution technique (DPDT). This technique is used on adders, booth multipliers. In this research proposes a pipelined variable precision gating scheme to improve the power awareness of the system.
A digital filter gives a digital output and consists of digital components. In a digital filtering application, software running on a DSP applications and reads the input samples from an A/D converter. It performs the mathematical manipulations dictated by the required filter type and output the result as D/A converter. An analog filter operates directly on the analog inputs and is built entirely with analog components such as resistors, capacitors, and inductors. There are many types of filter used in DSP applications, but the most commonly used filters are lowpass, highpass, bandpass, and bandstop. A low pass filter allows only low frequency signals (below some specified cutoff) through its output and it can be used to eliminate high frequencies. A low pass filter is small and for limiting the upper most range of frequencies in an audio signal. A high pass filter does the opposite of low pass filter by rejecting the frequency components below some threshold. An example high pass application is cutting out the audible 60Hz AC power "hum", which can be picked up as noise accompanying almost any signal in the U.S. The designer of a cell phone or any other sort of wireless transmitter would typically place an analog bandpass filter in its output RF stage to ensure only output signals. Engineers mostly use bandstop filters, because this filter passes both low and high frequencies to block a predefined range of frequencies in the middle. The Frequency response Simple filters are usually defined by their responses to the individual frequency components that constitute the input signal..


  1. AbdSamadBenkrid and Khaled Benkrid, “Novel Area- Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension” 2009.Ahmed F. Shalash, Keshab K. Parhi “Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications” Journal of VLSI Signal Processing, 2000.
  2. AnupHosangadi and Ryan Kastner “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method” 2006.
  3. A.RenukaNarasimha, K.Rajasekhar,A.Sujana Rani, “ Implementation of Low Area and Power Efficient Architectures for Digital FIR Filters” August 2012.
  4. BahmanRashidi, and Majid Pourormazd, “Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer” April 2013.
  5. C. N.Marimuthu, P. Thangaraj, “Low Power High Performance Multiplier ICGST-PDCS”, December 2008.
  6. I. C. Park and H. J. Kang, “FIR filter synthesis algorithms for minimizing the delay and the number of adders,” pp. 770– 777, Aug. 2001.
  7. Jin-Gyun Chung, Keshab K. Parhi “Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design” EURASIP Journal on Applied Signal Processing 2002.
  8. Kousuke TARUMI, Akihiko HYODO, Masanori MUROYAMA, Hiroto YASUURA, “A design method for a low power digital FIR _filter in digital wireless communication systems,” 2004.
  9. M. SreeDivya and G. Kiran Kumar “Implementation of Low Power Digital FIR Filter Design Based on Low Power Multipliers and Adders”, 2012.
  10. Ronak Bajaj, SaranshChhabra, SreehariVeeramachaneni, M B Srinivas, “A Novel, Low-Power Array Multiplier Architecture”, 2002.
  11. Senthilkumar and A. M. Natarajan, “FPGA implementation of power aware FIR filter using reduced transition pipelined variable precision gating,” Journal of Computer Science, pp. 87-94, 2008.
  12. ShahnamMirzaei, AnupHosangadi, Ryan Kastner, “FPGA Implementation of High Speed FIR Filters Using Add and Shift Method”, IEEE, 2006.
  13. T Ramesh Reddy, Dr. K. SoundaraRajan, “Low-area and power Digital FIR Filter Implementations”, 2012.
  14. W. Brian and M. Barr, “Introduction to digital filters,” Embedded System Programming, December 2002.