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An Efficient 4-Parallel Feed Forward FFT Architecture by using Multipath Delay Commutator

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Fast Fourier Transform (FFT) is widely used in the field of digital signal processing (DSP) such as filtering spectral analysis, etc, to compute discrete fourier transform. The appearance of radix-2 2 which had been a milestone in the design of pipelined FFT hardware architectures was later extended to radix-2 K.This project presents a new approach to develop parallel pipelined 16 point radix-2 2 . Feed forward (MDC) FFT architectures along with data shuffling. Furthermore, decimation in frequency (DIF) decomposition has been used. The power and area consumption can be reduced in 4-parallel FFT architecture. As a result, the proposed radix-2 2 feed forward architectures not only offer an attractive solution for current applications, but also open up new research line on feed forward structures. The output samples are obtained, to a desired order to implement on XILINXSPARTAN-3E FPGA.
Index Terms: Fast Fourier Transform (FFT), multipath delay commutator (MDC), pipelined architecture, radix-2k FPGA
The present day real time applications demand, the FFT to be calculated at very high throughput rates, These high performance requirements appear in applications such as millimeter Wave wireless local area network , wireless personal area network systems and real time video streaming services in short range indoor environments. The FFT/IFFT processor has a high hardware complexity in the OFDM modulation of high rate WPAN systems. One OFDM symbol in the IEEE 802.11ad standards consists of a length of 512 subcarriers. Therefore, FFT processor conducts the FFT computation with 512-point arithmetic and should provide a high throughput rate of at least 2.115 GS/s [1]. The radix of the algorithm greatly influences the architecture of the FFT processor and the complexity of the implementation. A small radix is desirable because it results in a simple butterfly. Nevertheless, a high radix reduces the number of twiddle factor multiplications. The radix 2k algorithms simultaneously achieve a simple butterfly and a reduced number of twiddle factor multiplications. The radix-2 algorithm is a well-known simple algorithm for FFT processors, but it requires many complex Multipliers. Recently various radix 2k FFT algorithms and architectures have been studied in order to reduce the number of complex this brief, a reconfigurable FFT architecture to compute 512-point FFT using radix-2k algorithm with the highspeed is proposed. The key ideas for achieving high date throughput, reduced hardware complexity are described .The power consumption and hardware cost can be saved in our processor by using the higher radix FFT algorithm and less memory and complex multipliers.
In this paper, a radix 2K algorithm and 512 point reconfigurable radix 2k FFT architectures have been proposed for OFDM-based WPAN applications. The use of radix 2k to feed forward (MDC) FFT architectures has shown that feed forward structures are more efficient than feedback ones when several samples in parallel must be processed. In feed forward architectures radix 2k -can be used for any number of parallel samples which is a power of two. Indeed, the number of parallel samples can be chosen arbitrarily depending of the throughput that is required. Additionally, both DIF and DIT decompositions can be used.


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